// **AUTOGENERATED FILE** **DO NOT EDIT**
// Generated by techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py
`timescale 1ns /10ps

module TDP36K_BRAM_A_X1_B_X1_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X1_B_X2_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X1_B_X4_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X1_B_X9_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X1_B_X18_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X1_B_X36_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X2_B_X1_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X2_B_X2_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X2_B_X4_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X2_B_X9_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X2_B_X18_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X2_B_X36_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X4_B_X1_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X4_B_X2_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X4_B_X4_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X4_B_X9_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X4_B_X18_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X4_B_X36_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X9_B_X1_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X9_B_X2_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X9_B_X4_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X9_B_X9_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X9_B_X18_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X9_B_X36_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X18_B_X1_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X18_B_X2_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X18_B_X4_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X18_B_X9_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X18_B_X18_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X18_B_X36_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X36_B_X1_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X36_B_X2_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X36_B_X4_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X36_B_X9_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X36_B_X18_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A_X36_B_X36_nonsplit (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X1_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X2_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X4_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X9_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule

module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X18_split (
	RESET_ni,
	WEN_A1_i,   WEN_B1_i,
	REN_A1_i,   REN_B1_i,
	CLK_A1_i,   CLK_B1_i,
	BE_A1_i,    BE_B1_i,
	ADDR_A1_i,  ADDR_B1_i,
	WDATA_A1_i, WDATA_B1_i,
	RDATA_A1_o, RDATA_B1_o,
	FLUSH1_i,
	WEN_A2_i,   WEN_B2_i,
	REN_A2_i,   REN_B2_i,
	CLK_A2_i,   CLK_B2_i,
	BE_A2_i,    BE_B2_i,
	ADDR_A2_i,  ADDR_B2_i,
	WDATA_A2_i, WDATA_B2_i,
	RDATA_A2_o, RDATA_B2_o,
	FLUSH2_i
	);

	parameter [80:0] MODE_BITS = 81'd0;
	parameter [1024*36-1:0] RAM_INIT = 36864'bx;

	input  wire RESET_ni;
	input  wire WEN_A1_i, WEN_B1_i;
	input  wire REN_A1_i, REN_B1_i;
	input  wire WEN_A2_i, WEN_B2_i;
	input  wire REN_A2_i, REN_B2_i;

	(* clkbuf_sink *)
	input  wire CLK_A1_i;
	(* clkbuf_sink *)
	input  wire CLK_B1_i;
	(* clkbuf_sink *)
	input  wire CLK_A2_i;
	(* clkbuf_sink *)
	input  wire CLK_B2_i;

	input  wire [ 1:0] BE_A1_i,    BE_B1_i;
	input  wire [14:0] ADDR_A1_i,  ADDR_B1_i;
	input  wire [17:0] WDATA_A1_i, WDATA_B1_i;
	output wire [17:0] RDATA_A1_o, RDATA_B1_o;

	input  wire FLUSH1_i;

	input  wire [ 1:0] BE_A2_i,    BE_B2_i;
	input  wire [13:0] ADDR_A2_i,  ADDR_B2_i;
	input  wire [17:0] WDATA_A2_i, WDATA_B2_i;
	output wire [17:0] RDATA_A2_o, RDATA_B2_o;

	input  wire FLUSH2_i;

	TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram (
		.RESET_ni   (RESET_ni),
		.WEN_A1_i   (WEN_A1_i),   .WEN_B1_i   (WEN_B1_i),
		.REN_A1_i   (REN_A1_i),   .REN_B1_i   (REN_B1_i),
		.CLK_A1_i   (CLK_A1_i),   .CLK_B1_i   (CLK_B1_i),
		.BE_A1_i    (BE_A1_i),    .BE_B1_i    (BE_B1_i),
		.ADDR_A1_i  (ADDR_A1_i),  .ADDR_B1_i  (ADDR_B1_i),
		.WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i),
		.RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o),
		.FLUSH1_i   (FLUSH1_i),
		.WEN_A2_i   (WEN_A2_i),   .WEN_B2_i   (WEN_B2_i),
		.REN_A2_i   (REN_A2_i),   .REN_B2_i   (REN_B2_i),
		.CLK_A2_i   (CLK_A2_i),   .CLK_B2_i   (CLK_B2_i),
		.BE_A2_i    (BE_A2_i),    .BE_B2_i    (BE_B2_i),
		.ADDR_A2_i  (ADDR_A2_i),  .ADDR_B2_i  (ADDR_B2_i),
		.WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i),
		.RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o),
		.FLUSH2_i   (FLUSH2_i)
	);

	`ifdef SDF_SIM
	specify
		(negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		(posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0;
		(posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0;
		(posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0;
		(posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0;
		$setuphold(posedge CLK_A1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0);
		$setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0);
		$setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0);
		$setuphold(posedge CLK_A2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0);
		$setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, RESET_ni, 0, 0);
		$setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0);
		$setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0);
	endspecify
	`endif
endmodule
